1. Field of the Invention
The present invention generally relates to a semiconductor device and a manufacturing method for a semiconductor device. More particularly, the present invention relates to a semiconductor device in which an element region is formed in an SOI (silicon on insulator) layer isolated by means of an isolation trench and a MOSFET is formed in the thus formed element region, and a manufacturing method for such semiconductor device.
2. Related Arts
Conventionally, there have been two types of manufacturing methods for a semiconductor device of SOI structure; one method uses a lamination of semiconductor substrates for forming the SOI structure, and the other method uses a SIMOX substrate for forming the SOI structure. In the former method, as disclosed in the Japanese Unexamined Patent Publication No. 5-167050, a SiO.sub.2 film is formed on a semiconductor substrate having a rugged surface, the surface of SiO.sub.2 formed on the semiconductor substrate is polished and bonded to the other semiconductor substrate, the bonded surface is polished, and thereby an SOI layer having an element region on the rugged surface is formed.
However, this method using a lamination of semiconductor substrates has a problem in that the film thickness of the SOI layer is not uniform due to polishing. In order to solve this problem, some measures should be taken to achieve a uniform polishing such as a provision of a plurality of dummy layers.
In contrast to this method, in the latter method using a SIMOX substrate for forming an SOI layer, oxygen is ion implanted into a semiconductor substrate and thereby a buried oxide film is formed in the semiconductor substrate and an SOI layer is formed as an element region by using the buried oxide film. This method, unlike the method using a lamination of substrates, has an advantage in that the film thickness can be made uniform.
When element isolation is obtained in the method using a SIMOX substrate for forming an SOI layer, the mesa isolation method or the LOCOS isolation method is used. A construction obtained by the mesa isolation method is illustrated in FIG. 9, and a construction obtained by the LOCOS isolation method is illustrated in FIG. 10.
When the mesa isolation method is used, as illustrated in FIG. 9, an SOI layer 13 is formed as an element region by the formation of an isolation trench. In this case, the wiring capacitance between a gate wiring 18 in a field part in which the SOI layer 13 is not formed and a substrate 11 constitutes a series capacitance of a gate oxide film 17 and a buried oxide film 12. Therefore, if the buried oxide film 12 is thin or the buried oxide film 12 becomes thin due to wet etching with hydrofluoric acid in a specific process of manufacturing, a parasitic capacitance C1 becomes large to the disadvantage of high-speed operation as shown in FIG. 11.
FIG. 12 shows that an insulating material 16 such as SiO.sub.2 may be buried in the isolation trench. In this case, the wiring capacitance can be reduced due to the buried SiO.sub.2. If the width of the isolation trench is large, however, the isolating material can not be deposited so thick in the central part of the trench and results in a structure illustrated in FIG. 12, and the above problem that the wiring capacitance increase can not be solved.
On the other hand, when isolation is obtained by the LOCOS isolation method, the problem caused by the mesa isolation method can be solved. Usually, however, because an oxide film layer, which is called "bird's beak," extending in the transverse direction is formed in the peripheral part of the SOI layer 13, the width of the isolation region should be made larger than the width by the mesa isolation method, and this poses a problem of low integration degree. Therefore, for higher integration degree, the mesa isolation method is more effective.